반도체 소자 및 그 제조방법

Abstract

본 발명은 반도체 소자 및 그 제조방법을 개시한다. 개시된 본 발명은,반도체 기판의 리세스 게이트 형성 영역 및 소오스/드레인 형성 영역의 오버랩되는 반도체 기판 부분에 절연막이 형성된 것을 포함한다.
A semiconductor device and a method of manufacturing the same are provided to reduce electric fields between a gate pattern and an impurity diffusion region to minimize a leakage current. A semiconductor device comprises a gate(370), a source region(380), a drain region(390) and an insulating layer(302). The gate is positioned on a semiconductor substrate. The gate is protruded from an upper side of the semiconductor substrate. The source and drain regions are extended toward a lower part of the semiconductor substrate from an upper side of the semiconductor substrate. The source and drain regions are arranged in both sides of a gate pattern respectively. The source and drain regions are on the semiconductor substrate and overlapped with the gate. The insulating layer is arranged on the semiconductor substrate. The insulating layer is arranged in the source and drain regions. The insulating layer is surrounded by the source and drain regions.

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    US-9105574-B2August 11, 2015SK Hynix Inc.Electronic device comprising a semiconductor memory unit
    US-9660041-B2May 23, 2017SK Hynix Inc.Electronic device comprising a semiconductor memory unit